The present invention relates to testing of a semiconductor integrated circuit with a built-in self-test, and more particularly, to testing of a circuit having a multi-cycle path.
In conventional testing of a semiconductor integrated circuit having a multi-cycle path, a scan flipflop (hereinafter, abbreviated as an “SFF”) is allowed to hold the value thereof with a clock enable signal so that the held value is captured. U.S. Pat. No. 6,145,105 (FIGS. 3c, 4 and 5d) describes semiconductor integrated circuits having a multi-cycle path and test methods therefor.
FIG. 8 is a circuit diagram of a conventional semiconductor integrated circuit having a multi-cycle path, and FIG. 9 is a waveform diagram of this semiconductor integrated circuit. In this circuit, capture, hold and shift operations are implemented with SFFs as shown in FIGS. 7A to 7C. For example, an SFF 700 of FIG. 7A includes a selector 720 connected to a data input D of a data flipflop (hereinafter, abbreviated as a “DFF”) 710 and a selector 730 connected to the selector 720. The DFF 710 has a clock input CK and a data output Q. The selector 720 selects either input data d or an output signal 733 of the selector 730 according to a scan enable signal se. The selector 730 selects either a scan input signal si or an output signal 713 of the DFF 710 according to a clock enable signal ce. Whether the DFF 710 operates shift or hold is determined with the value of the clock enable signal ce. By holding the value of the SFF with the clock enable signal ce, the operation of the SFF during the test can be made slower than the clock rate in the actual operation. The above operation implemented by the SFF 700 of FIG. 7A can also be implemented by SFFs 740 and 750 of FIGS. 7B and 7C. FIG. 7D illustrates any of the SFFs shown in FIGS. 7A to 7C, and FIG. 7E illustrates an SFF receiving no clock enable signal.
The operation of the conventional semiconductor integrated circuit having a multi-cycle path and a test method thereof will be described with reference to the circuit diagram of FIG. 8 and the waveform diagram of FIG. 9.
In FIG. 8, a first SFF 11 has a data output q, from which paths extend through a logic circuit 40 to a data input d of a second SFF 22 and also to a data input d of a third SFF 31. A BIST controller 100 includes a controller 102, a scan enable generation section 103, a clock enable generation section 104, a random pattern generator (PRPG) 105 and a data compressor (MISR) 106. The scan enable generation section 103 supplies a scan enable signal se1 to a terminal se of the SFF 11 and a scan enable signal se2 to terminals se of the SFFs 22 and 31. The clock enable generation section 104 supplies a clock enable signal ce1 to a terminal ce of the SFF 11. The random pattern generator 105 supplies a signal si1 to a scan input terminal si of the SFF 11 and a signal si2 to a scan input terminal si of the SFF 22. The data compressor 106 receives the outputs q of the SFFs 11 and 31 at inputs so1 and so2, respectively.
The SFF 11 operates shift and hold repeatedly according to the value of the clock enable signal ce1 as shown in the waveform in FIG. 9. In the illustrated example, the clock enable signal ce1 goes Low and High every cycle of the clock signal ck. Therefore, data is held for the duration of one clock cycle after each shift operation. The SFFs 22 and 31, receiving no clock enable signal, do not hold data. In the SFF 11, shift is done at time t0, hold comes at time t1, and then capture is done at time t2. Therefore, the shift at the time t0 is the last shift for the SFF 11 before the capture. In the SFFs 22 and 31, shift is done at time t0, shift, not hold, continues at time t1, and capture is done at time t2. Therefore, the shift at the time t1 is the last shift for the SFFs 22 and 31 before the capture. The value at the output q of the SFF 11 immediately before the capture is that held at the time t0, and the capture is done at the time t2, two clocks after the time t0, in the SFFs 22 and 31 that receive the data from the SFF 11 via the logic circuit 40. Thus, testing for the paths from the SFF 11 to the SFFs 22 and 31 receiving the data via the logic circuit 40 is performed at multi-cycle timing. In this way, the time length from the last shift to capture is extended to more than one clock cycle by providing hold for the SFF 11 during shift and immediately before capture using the clock enable signal ce and the scan enable signal se.
However, by holding the value of the SFF 11 with the clock enable signal ce as described above, data is captured at multi-cycle timing for all the paths from the output q of the SFF 11 to the data inputs d of the SFFs 22 and 31 for receiving data via the logic circuit 40. Therefore, even for a normally non-multi-cycle (single-cycle) path among the paths from the data output q of the SFF 11 to the SFFs 22 and 31 for receiving data via the logic circuit 40, data is captured at multi-cycle timing. For example, when the path from the data output q of the SFF 11 to the input d of the SFF 22 via the logic circuit 40 normally operates at multi-cycle timing while the path from the data output q of the SFF 11 to the input d of the SFF 31 via the logic circuit 40 normally operates at single-cycle timing, even the latter path to the SFF 31 that normally operates at single-cycle timing will be tested only at the multi-cycle timing. As a result, while the multi-cycled path can be tested in the actually used state, no actual operation speed check is available for the path normally operating at single-cycle timing.